The present invention relates generally to semiconductor devices and the manufacture thereof. More particularly, the present invention relates to a method of forming metal-oxide-semiconductor field effect transistors (MOSFETs) having copper metallization on a polysilicon gate.
The need has been recognized for improved metallization systems in next generation semiconductor devices. Reduced line widths and film thicknesses have resulted in excessive resistivity in current metallization systems. Copper, has a very low resistivity and is under development for second and third level metal layers on integrated circuits. However, heretofore, copper has been avoided for first level metallization. Copper has a high diffusivity in silicon which complicates formation ohmic contacts between copper and silicon or polysilicon. Accordingly, materials such as suicides have instead been used for contact formation and the use of copper interconnect has been limited to upper level metal layers.
U.S. Pat. No. 6,015,747 discloses an advanced metallization system in which electroless metal is selectively deposited on the gate and on the source and drain regions. U.S. Pat. No. 6,015,747 is incorporated herein by reference. This provides distinct advantages for reducing bridging of the gate metal and the source/drain metal. However, the techniques described therein are not adapted to metallization with highly conductive metals such as copper. Accordingly, there is a need for an improved method for manufacturing semiconductor devices with highly conductive metal at the first level or interconnect metal.
By way of introduction only, the present embodiments provide improved metallization in a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The method involves forming spacers on opposing sides of a polysilicon gate formed on the surface of the semiconductor. A trench is then formed between the spacers by selectively etching the polysilicon. Highly conductive metal such as copper is then deposited in the trench to form a copper-polysilicon gate. In an additional embodiment, electroless metal is deposited to form electrical contacts with the copper-polysilicon gate and the source/drain regions of the transistor. In a further embodiment, an electroless barrier metal layer is formed on the copper-polysilicon gate and a blanket of nickel or other similar metal is deposited on the surface of the semiconductor. The nickel is annealed to form nickel silicide on the exposed source/drain regions of the MOSFET. In a still further embodiment, nickel or similar metal is blanket deposited on the substrate including the copper-polysilicon gate. A copper-nickel alloy is formed on the copper-polysilicon gate and nickel-silicide is formed at the source/drain regions.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.